Computerintroduction
ReducedInstructionSetComputing(RISC:ReducedInstructionSetComputing)isacomputerwithashorterinstructionlength,anditsoperatingspeedFasterthanCISC.RISCandCISCareCPUsthatcanbedividedintotwocategoriesfromthecharacteristicsoftheinstructionset:CISCandRISC.RISCistheabbreviationofEnglishReducedInstructionSetComputing,whichis"reducedinstructionoperationset",CISCis"complexinstructionoperationset".TheinstructionsystemofRISCisrelativelysimple.Itonlyrequiresthehardwaretoexecuteverylimitedandmostcommonlyusedinstructions.Mostofthecomplexoperationsusematurecompilationtechnologyandaresynthesizedbysimpleinstructions.Atpresent,theCPUofthisinstructionsystemiscommonlyusedinmiddleandhigh-endservers,especiallythehigh-endserversallusetheCPUoftheRISCinstructionsystem.TheCPUsthatuseRISCinstructionsinmid-to-high-endserversmainlyincludeAlphafromCompaq(Compaq,thenewHewlett-Packard),PA-RISCfromHP,PowerPCfromIBM,MIPSfromMIPS,andSparcfromSUN.
RISCisrelativetothecomplexinstructionsetcomputer(CISC).Theso-calledcomplexinstructionsetcomputerreliesonincreasingthehardwarestructureofthemachinetomeettheincreasingperformancerequirementsofthecomputer.Thedevelopmentofcomputerstructurehasalwaysbeenmonopolizedbyprocessorswithincreasingcomplexity.Inordertoreducethedifferencebetweencomputeroperationsandhigh-levellanguages,inordertoimprovetheoperatingcharacteristicsofthemachine,therearemoreandmoremachineinstructionsandmoreandmorecomplexinstructionsystems..Especiallythecontradictionbetweentheearlierhigher-speedCPUandtheslower-speedmemory.Inordertominimizethenumberofaccesstodataandincreasethespeedofthemachine,acomplexinstructionsethasbeengreatlydeveloped.However,withthedevelopmentofsemiconductorprocesstechnology,memoryThecontinuousincreaseinspeed,especiallytheuseofhigh-speedbuffers,hascausedfundamentalchangesinthecomputerarchitecture.Whilethehardwaretechnologyhasimproved,thesoftwarehasalsoundergoneequallyimportantdevelopments,andoptimizedcompilershaveappearedtoenabletheexecutionofprograms.Timeisreducedasmuchaspossible.Andtominimizethememoryoccupiedbymachinelanguage,withadvancedmemorytechnologyandadvancedcompilerconditions,theCISCarchitectureisnolongerapplicable,sotheRISCarchitecturewasborn.ThebasicstartingpointoftheRISCtechnologyistoadoptReducethemachineinstructionsystemtoreducethecomplexityofhardwaredesignandincreasethespeedofinstructionexecution.InRISC,thecomputeractuallyexecutesinstructionsineverymachinecycle.Nomattersimpleorcomplexoperations,theyareallcompletedbyprogramblocksofsimpleinstructions,whichhasstrongsimulationcapabilities.
InaRISCmachine,itisrequiredtoexecuteallinstructionswithina"singlemachinecycle"time,andthemostfundamentalthroughputlimitofthesystemisdeterminedbytheproportionofthememoryaccesstimeduringprogramoperation.Therefore,aslongasTheCPUexecutiontimeisthesameastheinstructionfetchingtime,andthemaximumsystemthroughputratecanbeobtained.(Foramachinecycletoexecuteaninstruction).InRISCmachines,hardwarecontrolisusedtoachievefastinstructiondecoding,andfewerinstructionsandsimpleaddressingmodesareadopted,andinstructiondecodingandhard-wiredcontrollogicaresimplifiedthroughafixedinstructionformat.Inaddition,RISCdesignisbasedoncomplexcompilationdesignoptimizationtoobtainasimplehardwarechipenvironment.CompileroptimizationcanimprovetheoperatingefficiencyofHLLprograms,butallprogramsmustbewritteninhigh-levellanguages.
RISCdesigneliminatesmicrocoderoutines,andhandsthelow-levelcontrolofthemachinetosoftware.Thatis,usingfasterRAMinsteadofthemicrocodeROMintheprocessorastheinstructioncache(Cache),thecomputer'scontrolresidesintheinstructioncache,sothattheinstructionstreamgeneratedbythecomputersystemandthecompilercanmeettherequirementsofhigh-levellanguageandhardwareperformanceWorkcloselytogether.
Theperformanceofacomputercanbemeasuredbythetimerequiredtocompleteaspecifictask,whichisequaltoC×T×I.
C=thenumberofcyclesrequiredtocompleteeachinstruction,T=thetimeofeachcycle,I=thenumberofinstructionspertask
RISCtechnologyistomakeCandTMinimized,thereductionofCandTmayleadtoanincreaseinI,buttheuseofoptimizedcompilationtechniquesandothertechnologiescanmakeupfortheimpactoftheincreaseinIonmachineperformance.ThereasonwhyRISCtechnologyhasrapidlydevelopedfromanewinsightintoapromisingcomputermarketismainlyduetothefollowingreasons:oneisthattheRISCstructureadaptstotherapiddevelopmentofVLSItechnology;theotheristhatRISCsimplifiestheprocessorstructure,implementationanddebuggingItiseasier,sothedesigncostislow,andthedevelopmentcycleisshort;thethirdistosimplifythestructure,andtheprocessoroccupiesasmallerchiparea,sothatlargerregisterfilescanbeintegratedonthesamechip,translationbackupbuffer(TLB),Coprocessorsandfastmultipliersanddividers,etc.,enabletheprocessortoobtainhigherperformance;fourth,RISC'ssupportforHLLprogramsisbetterthanpreviouscomplexinstructionsystemcomputers,allowingusers(programmers)toeasilyuseaunifiedinstructionset.Itiseasytoestimatetheeffectofcodeoptimization,sothatprogrammershavemoreconfidenceinthecorrectnessofthehardware.
Classification
Usingmulti-levelinstructionpipelinestructure
UsingpipelinetechnologycanmakemultipleinstructionsoverlapexecutionateverymomenttoreducethevalueofCPI,SothattheCPUdoesnotwasteemptycycles.Example:PentiumⅡ/Pro/Celeroncanissueandexecutefiveinstructionsatthesametime,AMD-K6/K6-2canissuesixinstructionsatthesametime.
Simpleinstructionsandsomecomplexinstructionswithhighfrequencyinthemachine
ThiscanreducethenumberofclockcyclesandincreasetheCPUspeed.TheessenceistoreducethevalueunderCPI.Example:Choosearithmeticinstructions,load,storeinstructions,andtransferinstructionsasthemaininstructionset.
UsingLoadandStorestructures
OnlytheLoadandStoreinstructionsareallowedtoperformmemoryoperations,andtherestoftheinstructionsalloperateonregisters.Examples:Amd-K6/K6-2,PⅡ/Celeron/Proallsupportdirectoperationandrenamingofregisters,andgreatlyincreasethenumberofgeneral-purposeregisters.
Delayedloadinstructionsandtransferinstructions
Becauseofthespeeddifferencebetweenthetwodatafromthememorytotheregister,thetransferinstructionsneedtocalculatetheentryaddress,whichgreatlylimitstheexecutionspeedoftheCPU.Therefore,inordertoensurethehigh-speedoperationofthepipeline,RISCtechnologyallowsanirrelevantimmediatelyexecutableinstructiontobeaddedbetweenthemtoincreasethespeed.
Example:Mainlyreflectedinpredictiveexecution,non-sequentialexecutionanddatatransmission,etc.,exceptIntelP54/55Cdoesnotsupport,likeK6-2,PⅡsupport.
Usingacachestructure
InordertoensuretheuninterruptedtransmissionofinstructionstotheCPUarithmeticunit,theCPUhassetupacertainsizeofCachetoexpandthebandwidthofthememoryandmeettherequirementsoffrequentCPUfetching.Referstorequirements,generallytherearetwoindependentCaches,whichstore"instructions+data"respectively.
Example:PⅡ/Celeron:16K+16K,AMD-K6/K6-2is32K+32K,CyrixMⅡ:64K(actuallytwo32KCaches,thisisusedasasharedCache),PⅡalsoaddsL2Cache,whichgreatlyimprovestheCPUspeed.
FeaturesofRISC
ThefeaturesofRISCarethattherearefewinstructionsandformats,simpleoperationandcontrol.Specifically,therearethefollowingaspects.
Simplifiedinstructionset
TheRISCstructureadoptsasimplified,long-shortinstructionset,whichenablesmostoperationstoobtainthehighestpossibleefficiency.Someoperationsthatneedtobeimplementedwithmulti-cycleinstructionsinthetraditionalstructurearereplacedbymultiplesingle-cycleinstructionsintheRISCstructurethroughmachinelanguageprogramming.ThesimplifiedinstructionsethasgreatlyimprovedtheperformanceoftheprocessorandpromotedthedesignofRISC.Thereisnodefiniteanswertothequestionofhowsimpleitis.ComparingtheexistingRISCsystemwiththeCISCsystem,wecanseethegeneralsituation.Generally,forRISC:
Thenumberofinstructionsissmall,nomorethan128.
Therearefewaddressingmodes,nomorethan4kinds.
Therearefewinstructionformats,nomorethan4types.
Itisveryprudenttodealwiththesuggestionsontheexpansionoftheinstructionset.Itmustbecarefullyweighedandverifiedtoseeiftheycanreallyimprovetheperformanceofthecomputer.Forexample,MIPSadoptsarule:addinganinstructionmustmaketheperformancegain1%withinacertainapplicationrange,otherwisethisinstructionwillberejected.
Instructionclockcycle,instructionlengthisequal
Ifthetasktobeexecutedbyeachinstructionissimpleandclear,thetimerequiredtoexecuteeachinstructioncanbecompressedorreducedbythenumberofcycles.ThedesigngoalofRISCistoimplementamachinecycletoexecuteaninstruction,makingthesystemoperationmoreefficient.Technologiesthatapproachthisgoalincludeinstructionpipelinesandspecificinstallation/storagestructures.Atypicalinstructionmayincludethestagesoffetching,decoding,executing,andstoringresults.Single-cyclemeanscanbeachievedbymakingallinstructionsthestandardlength.Thestandardinstructionlengthshouldbeequaltothebasicwordlengthofthecomputersystem,usuallyequaltothenumberofdatalinesinthesystem.
Inanyinstructionfetchcycle,acompletesingleinstructionmustbepassedtotheCPU.Forexample,ifthebasewordlengthis32bitsandthedataportionofthesystembusis32lines,thestandardinstructionlengthis32bits.Itisdifficulttomaketheexecutiontimeofallinstructionsconsistent.Someinstructions,includingsimplelogicoperationsonCPUregisters(clearingregisters,etc.),canbeeasilyexecutedwithinoneCPUclockcycle;otherinstructionsmayincludememoryaccess(readingandwritingtomemory,fetching,etc.)orMulti-cycleoperations(multiplication,division,etc.)maynotbeexecutedinasinglecycle.Thisputsforwardsucharequirementtothedesigner;allowsmostfrequentlyusedinstructionstobeexecutedinasinglecycle.
Instructionpipeline
Thewaytoreducethenumberofcyclesrequiredtoexecuteaninstructionistoexecutemultipleinstructionsoverlapped.Theinstructionpipelineusessuchaworkingmethod:theexecutionofeachinstructionisdividedintoseveraldiscreteparts,andthenmultipleinstructionsareexecutedatthesametime.Thefetchandexecutionphasesofanyinstructionoccupythesametime,ideallyasinglecycle.ThiscanbesaidtobethemostimportantdesignprincipleofRISC.AllinstructionsexecutedfromthememorytotheCPUfollowaconstantflow.Eachinstructionisexecutedatthesamepace,nowaitinginstructions.TheCPUisalwaysbusy.Thenecessaryconditionstoachievepipelineoperationare:
Standard,fixed-lengthinstructions,whichareequaltothewordlengthofthecomputerandthewordlengthofthedataline.
ThestandardexecutiontimeofallinstructionsispreferablywithinasingleCPUcycle.
Forexample,theSPARCchipadoptsafour-stagepipelinestructureforfetching,decoding,executingandwritingresultstomaximizeprocessorperformance.Atthebeginningofeachclockcycle,anewinstructioncanbeexecuted,whichensuresthatanewinstructionisfetchedfromthememoryineachmachinecycle.Therefore,ingeneral,mostinstructionscanbeexecutedinasinglecycle.accomplish.Instructionpipelinetechnologycanbecomparedtoanassemblyline-instructionsarelikeprocessedproducts,fromoneprocesstothenext,untilitisexecuted.
Therefore,itispossiblefortheinstructionpipelinetouseafactorequaltoitspipelinedepthtoreducethenumberofinstructioncycles,butinthiscase,itisrequiredthatthepipelineisalwaysfilledwithusefulinstructionsandnothingpreventsinstructionsfrompassingthroughthepipeline.Demandputsacertainburdenonthestructure.Forexample,competitionforresourcessuchasALUpreventstheflowofinstructionsinthepipeline.Theundesirableconsequencescausedbytheexecutiontimeofdifferentlengthsareevenmoreobvious,whichiswhyRISCdefinesaninstructionsetwiththecharacteristicsdescribedabove.
Loadandstore(LOAD/Store)structure
Toexecutememory-relatedoperationinstructions,itisnotrequiredtoincreasethetimeofeachcycleorthenumberofcyclesofinstructions.Oneofthetwomustbechosen.Becausetheseinstructionsneedtocalculatetheaddressoftheoperand,readtherequiredoperandfromthememory,calculatetheresult,andthensendtheresultbacktothememory,theirexecutiontimeismuchlonger.Inordertoeliminatethenegativeeffectsofsuchinstructions,RISCadoptssuchaloadandstorestructure:onlyLoadandStoreinstructionscanaccesstheinter-memory,andallotheroperationsonlyaccesstheregistersstoredintheprocessor.Theoperandin.Itsadvantagesare:
Reducethenumberofaccessestomemoryandreducetherequirementsformemorybandwidth.
Alloperationsarerestrictedtoregistersonly,whichhelpssimplifytheinstructionset.
Cancelingmemoryoperationsmakesiteasierforthecompilertooptimizeregisterallocation—thisfeaturereducesmemoryaccessandalsoreducesthenumberofinstructionspertask.
AllthesecontributetoRISC'sgoalofexecutingoneinstructionpercycle.Nevertheless,loadandstoreinstructionsstillhindertherealizationofIRSC'sdesigngoals.Theuseofoptimizedcompilationtechnologytodealwiththedelayofloadinstructionsandbranchinstructionscanhelpsolvetheproblem.AlthoughoptimizingcompilationtechnologyisnotspecificallyorientedtoRISCstructures,optimizingcompilersrelyonRISCstructurestocompletetheiroutstandingtasks,andRISCstructuresrelyonoptimizingcompilerstogettheirbetterperformance.Theinterpretermustbeabletoanalyzethedataandcontrolflow,andadjusttheorderofexecutionofinstructionsonthisbasis,andcleverlyarrangetheusageofregisters.TheformerfunctioncanreducetheidletimeoftheCPU,andthelatterfunctioncanincreasethereusabilityrateofthedatastoredintheregister,reducethenumberofmemoryaccesses,andshortenthelengthofthedatapath.
Havealargerregisterset
Inordertofacilitatetherealizationoftheoperationofmostinstructionsbetweenregisters,thatis,theso-calledregister-to-registeroperation,theremustbeasufficientamountofCPUgeneral-purposeregisters.AsufficientamountofregistersmakesitnecessarytotemporarilystoretheintermediateresultsforoperationsintheCPUregistersinsubsequentoperations,thusreducingtheloadingandstoringofthememory,andspeedinguptheoperation.Atleast32general-purposeCPUregistersareusedinindustrializedRISCsystems.
Usinghard-wiredcontrol
Duetotheflexibilityprovidedbymicroprogrammingtodesigners,manyCISCsystemsarecontrolledbymicroprogramming.Differentinstructionsusuallyhavedifferentlengthsofmicroprograms,whichmeansthatthenumberofcyclesexecutedbyeachinstructionisdifferent,whichcontradictstheconsistentandstreamlinedprocessingprincipleofallinstructions.Butthiscanbesolvedbyhard-wiredcontrol,andthespeedwillbefaster.Therefore,RISCshouldbecontrolledbyhard-wiredwires.Theremaybeexceptionswheneachinstructionhasaone-to-onecorrespondencewithasinglemicro-instruction,thatis,eachmicro-programconsistsofasinglecontrolword.Thisdesigncanbeasfastandasefficientashard-wiredcontrol,andallowsdesignerstobenefitfromtheadvantagesofmicroprogramming.Usinghard-wiredcontrolmakestheRISCsystemcontrollersimple.Thesimplicityofthedesignmakesthelayoutofthemachinemorereasonable,allowingthedesignertoconcentrateonoptimizingtheremaining,few,butcriticalprocessorfeatures.Thesimplifiedstructurerelievestheshortageofarearesourcesonthechip.Somestructuresthatarecriticaltoperformance,suchaslargeregistercomponents,conversionlookupbuffer(TLB)Scoprocessor,andmultiplicationanddivisionunitcanallbeinstalledonthesamechip..Theseadditionalresourcesaddagreatperformanceadvantagetotheprocessor.Infact,RISCdoesnotnecessarilyhavetheabovecharacteristicsstrictly,andsomesystemscalledRISCevenviolatesomeoftheaboveaspects.TheabovecharacteristicsshouldbeusedasaguidingprincipletoexplainthenatureofRISC.Torelax,asystemthatsatisfiesmostofthesecharacteristicscanberegardedasaRISC.
Advantages
RISCcanimprovespeedwhilekeepingcostsdown.
ApplicableVLSI(VERYLARGESCALEINTEGRATION)process.
BecausetheRISCinstructionsetisclearandsimple,itonlyneedsarelativelysmallandsimplecontrolunitdecodingandhardwareexecutionsubsystem.ThisleadstothefollowingresultswhenusingVLSItoimplementcomputersystems:
Thechipareaoccupiedbythecontrolunitisgreatlyreduced.Forexample,RlsCIaccountsfor10%,whileCISCusuallyaccountsformorethan50%..Therefore,intheRISCVLSIchip,morefreespaceisleft,sothattheentireCPUandothercomponentsareononechip(suchascache,floating-pointunit,partofthemainmemory,memorymanagementunit,1/0port).
Becausethecontrolareaisreduced,itispossibletoincreasetheamountofCPUregisters(138forRISCI)onthechip.
ByreducingtheareaofthecontrolunitontheVLSIchipandplacingalargenumberofconsistentregisters,theregularizationfactor(regulariZationfaetor)ofthechipcanbeimproved.Basically,thehighertheregularizationfactor,thelowertheVLSIdesigncost.
ItisbeneficialtouseGaAs(galliumarsenide)VLSIchipimplementationtechnology,becauseitissuitableformanufacturinghigh-densitychips.Inshort,itreducesthecomplexityoftheprogramandsimplifiesthestructure.
Highspeed.
OneofthecharacteristicsofRISCistheinstructionpipeline,andtheconsistencyofinstructionlengthandexecutiontimeminimizesthewaitingandholdingtimeinthepipeline.Thesefactorshelpincreasethecalculationspeed.ThesimplerandsmallercontrolunitinRISCalsohasfewerdoors,whichmakesthesignaltransmissionpathofthecontrolunitshorterandspeedsuptheoperation.Thesimplificationoftheinstructionsetresultsinasmallandsimpledecodingsystem,whichcanspeedupthedecodingspeedofRISC.ThereductionofcontrolunitsbyhardwiringmakesRISCperformfasterthansystemsusuallycontrolledbymicroprograms.TherelativelylargeCPUregisterreducestheconflictsbetweenCPUandmemoryinfetchinginstructionsandstoringnumbers;thelargeregistergroupcanbeusedtostoretheparameterspassedbetweenthecallingprocessandthecallingprocess,andstoretherelevantinformationoftheinterruptprogram,otherwise,Thisinformationcanonlybestoredinmemory.Allthesesavealotofcomputerprocessingtime.Thebranchdelaytechniqueinoptimizingcompilationalsocontributestotheincreaseinspeed.Ingeneral,RISCisgenerally2to4timestheprocessingspeedofCISCwhenthefunctionsareroughlythesame.
Reducedesigncostandimprovereliability
CPUisrelativelysmallandsimplecontrolunitItusuallyleadstothefollowingcostandreliabilitybenefits:a.ThedesigntimeoftheRISCcontrolunitisshortened,whichcanreducetheoveralldesigncost.b.Theshortdesigntimereducesthepossibilityofthefinalproductbeingdiscardedwhenthedesigniscompleted.c.Simpler,smallercontrolunitcanreducedesignerrors,therebyimprovingreliability;moreover,itiseasiertolocateandcorrecterrorsthanCISC.d.Becausetheinstructionformatl(or2types)issimpleandfew,allinstructionshaveastandardlength,sotheinstructionwillnotcrossthewordboundary,norwillitcrossdifferentpagesinthevirtualmemory(iVrtualMemory),whichexcludesvirtualmemorymanagementPotentialdifficultiesinsubsystemdesign.
Supporthigh-levellanguage,butnotassemblylanguage
TheevolutionfromCISCtoRISCTheprocessissimilartothedevelopmentprocessofassemblylanguagetohigh-levellanguage.Writingaprograminassemblylanguageneedstousesomewell-designedcomplexinstructions,whilewritingahigh-levellanguageisalmostdifferentfromcomplexinstructions.Whilepursuingstreamlinedinstructions,RISCcloselyintegratesthedesignofthearchitectureandoptimizedcompilation,sothattheintegratedresultsleadtotheimprovementofoverallperformance.IfthedevelopmentofRISCisbasedontheimprovementofVLSItechnologyandcompilationtechnology,itcanbeunderstoodasreplacingthecomplexinstructionsystemwithcomplexcompilation,anditcanevenberegardedasthetransferofhardwareproblemstosoftware.Inrecentyears,therapiddevelopmentofintelligentcompilerscaneasilyperformthistask.PerhapstheadvantageofRISCliesinthis.TraditionalCISCmusthavecomplicatedmicrocodewritinganddesignwork,andtheuseofassemblylanguagealsoinvolvesthedevelopmentofassemblyprograms,whichareverylabor-intensiveandtime-consuming.RISCismoreconducivetosupportinghigh-levellanguages,whichisalsooneofthewaystosolvethe"softwarecrisis"facedbycomputersforalongtime.ThesuccessofRISCliesinsoftwarecompatibility.Aslongasthesource-levelcompatibilityismadethroughrecompilation,theexistingsoftwarecanbeeasilyrunontheRISCmachine.
Benefitsforprogrammers(users)
ThesimplifiedstructureenablesprogrammersAlsogotmanybenefits:
Amoreunifiedinstructionsetisveryconvenienttouse.
Sincethereisarelativelystrictcorrespondencebetweenthenumberofinstructionsandthenumberofcycles,theactualeffectofcodeoptimizationcanbeeasilymeasured.
Programmershaveamoreaccurategraspofhardware.
Disadvantages
Thereisanupsurgeinthecomputerworldtofindbetterperformance.RISCandCISCarebothconfrontingandcomplementary.RISChasitsownshortcomings.
Thelengthoftheinstructionsaftercompilationislonger,andthememoryneedstobelarger
TheshortcomingsofRISCaredirectlyrelatedtosomeofitsadvantages.BecauseRISChasasmallnumberofinstructions,somefunctionsthatcanbecompletedbyonlyoneinstructioninCISCrequiretwo,threeormoreinstructionsinRISC,whichmakestheRISCcodelonger,soRISCprogramsrequiremorememory.InstructionconflictsbetweenmemoryandCPUwillalsoincrease.Researchshowsthat,onaverage,toperformthesamefunction,aRISCprogramis30%longerthanaCISCprogram.Atthesametime,RISChashigherrequirementsforcompilers.Thedesignofoptimizingcompilersisaverycomplexandtechnicallydemandingwork.ItmustbecompiledbytheRISCmachinemanufactureritself,becauseitisimpossibletogenerateacompilationwithoutdetailedRISCoriginaldata.Theobjectcodeoftheprogram.Inthisway,itismoredifficultforthird-partycompaniestoprovidenewversions,usershavelesschoice,andsoftwarecostsincrease.
Largeregisterbankmakesaddressingcomplicatedandslowsdown
AcontroversialfeatureofRISCsystemisitslargeregisterbank.Thelargeregisterbankhastheaforementionedadvantages,butontheotherhand,therearealsodisadvantages.Thelargeregisterincreasestheaddressingtime.Ontheotherhand,somecompilersmaketheuseofthesmallregisterbankmoreeffective.HowbigtheCPUregisterbankshouldberemainstobediscussed,andthelargeregisterUbankcanalsobereplacedbyacache(CACHE).Theshortcomingsofthelargeregisterbankcanbesummarizedasfollows:
Longaccesstime.
Theregisterbankoccupiesmorechipspace.
Advancedcompilationtechnologymakesthesmallregisterbankmoreeffective.
IfallCPUregistersinthecontextswitchscenearesaved,thelargeregisterbankwillsavemorestoragetime.
Ifawindowpointerisused(oneofthekeypointsintheimplementationofRISCistooverlaptheregisterwindow,thepurposeistofacilitateparametertransfer.Theoverlapregisterwindowneedstousethewindowpointer),registeraddresstranslationThecodewillbelonger.Atthesametime,overlappingregistersalsocomplicatetheCPUlogic.
Thehard-wiredcontrolisnotflexible
Thereisagreaterpossibilityoferrors,anditisnoteasytofindandmodifyerrors,anddealwiththemComplexinstructionsarealsomoredifficult.(4)Single-wordinstructionscannotusedirectmemoryaddressingforfull32-bitaddresses.Forthisreason,somemanufacturershavemadeasmallnumberofinstructionswithdouble-wordcards(suchasINTEL80960).Theuseofsuchinstructionsisuptotheprogrammertowritecompleteprogramswithonlysingle-wordinstructions.
Developmentprospects
ThebasicstartingpointofRISCtechnologyistoreducethecomplexityofhardwaredesignandincreasethespeedofinstructionexecutionbystreamliningthemachineinstructionsystem.AlthoughRISC'sdesignideashavehadahugeimpactonthecomputerstructureandachievedgreatsuccess,thecomplexinstructionsetcomputer(CISC)technologymakestheprogrammingoftheprogramrelativelyeasier.Therefore,theCISCtechnologyandtheRISCtechnologyarenotcompatible.Theyarenotisolatedfromeachother.Atpresent,thereisanewdesignidea,whichisbasedonimprovingtheperformanceoftheentirecomputersystem,andhasabsorbedtheadvantagesofCISCandRISCinstructure.Forexample,RISCtechnologyisusedinmanyCISCdesigns.TheNSC32532microprocessorofNationalSemiconductorCorporationadoptsRISCtechnologyinCISCdesign,whichreducestheaverageexecutiontimeofinstructionsfromtheoriginal6machinecyclestolessthan2.4machinecycles.Underthemainfrequencyof26MHZ,theoperatingspeedcanreach10-12M1PS.Intel80486andMot.r.la68040alsoabsorbsRISCdesigntechnology,sothattheaverageexecutiontimeofeachinstructionislessthan2machinecycles.Fairchild'sClippermachineisa32-bitmicroprocessorthatintegratestheadvantagesofR1SCandCISCtechnology,anditsrunningspeedisashighas33MIPS.Therefore,thecurrenttwomainmethodsofdesigningprocessors(RISCandClSCtechnology)arenotcompletelyseparate.Theyarecomplementarytoeachother.Atpresent,peoplehavecombinedCISCtechnologyandRISCtechnologytoproposeawritableinstructionsetcomputer(WISC)structuredesign,andspecifythestrategicprinciplesofconcentratingtheadvantagesofRlscandClsc,nevertheless,itisstillafurtherreleaseofaRISCtechnicaldogbasedontheconceptofRlSC.
Atpresent,mostRISCprocessorshavereachedthegoalofexecutingoneinstructionpercycle(ieCPIratio),butthisisnotthelimit.SuperscalarandsuperpipelinetechnologyhaveappearedinRISCtechnology.Superscalartechnologyistomakethemicroprocessorexecuteseveralinstructionsinparallelinoneclockcycle,whilesuperpipelinetechnologyisthatthemainstreampipelinesegment(instructiondecodingandinstructionexecution)onlyoccupiesapartofoneclockcycle,sothatitcanstillbeSeveralinstructionsIntel8096areexecutedsimultaneouslyinoneclockcycle.Itusessuperscalartechnology,whichcanexecuteintegerinstructionsandfloatingpointinstructionsatthesametime.IBM'sRS/6000alsousesasuperscalarstructure,theprocessorcontainsthreedifferentprocessingcomponents:fixed-pointprocessor,floating-pointprocessor,Branchprocessor,oneclockcyclecanexecutefourinstructions(4IPC),upto6IPc.RIScscientistspointedoutthattheencouragingprocessofimprovingmicroprocessorperformanceinthepastisunlikelytocontinue.Inthefuture,Cachecapacityanditsstructureandoptimizedcompilerwillbecomekeyfactorsinimprovingcomputerperformance.Thefocusoffuturedevelopmentwillbeonmulti-processortechnology.