bus

Howitworks

IftheMotherBoardisacity,thenthebusislikeabusinthecity,whichcanbetransmittedbackandforthaccordingtoafixedroute.Operatingbit(bit).Alinecanonlyberesponsiblefortransmittingonebitatthesametime.Therefore,multiplelinesmustbeusedatthesametimetotransmitmoredata,andthenumberofdatathatthebuscantransmitatthesametimeiscalledwidth,inbits,thelargerthebuswidth,thebetterthetransmissionperformance.Thebusbandwidth(thatis,thetotalnumberofdatathatcanbetransmittedperunittime)is:busbandwidth=frequencyxwidth(Bytes/sec).Whenthebusisidle(otherdevicesareconnectedtothebusinahigh-impedancestate)andadevicewantstocommunicatewiththetargetdevice,thedevicethatinitiatesthecommunicationdrivesthebusandsendsoutaddressesanddata.Ifotherdevicesconnectedtothebusinahigh-impedancestatereceive(orcanreceive)theaddressinformationthatmatchestheirown,theywillreceivethedataonthebus.Thesendingdevicecompletesthecommunicationandgivesupthebus(theoutputbecomesahighimpedancestate).

Apubliclineorchannelusedinacomputertoconnectvariousfunctionalcomponentsandtransmitdatabetweenthem.Accordingtotheconnectedobjectsinthecomputersystem,thebuscanbedividedinto:Chipbus,alsoknownasthedevice-levelbus,whichisthebusinsidethecentralprocessingunitchip.Internalbus,alsoknownassystembusorboard-levelbus,isthetransmissionpathbetweenthefunctionalunitsofthecomputer.Microcomputerbusisusuallycalledinternalbus.Externalbus,alsoknownascommunicationbus,isatransmissionpathbetweencomputersystemsorbetweenacomputerhostandperipheraldevices.

Thebusisashareddatatransmissiondevice.Althoughmultipledevicescanbeconnectedtothebus,usuallyonlyonepairofdevicescanparticipateindatatransmissionatanyonetime.Accordingtotheformofinformationtransmission,thebuscanbedividedintotwotypes:parallelbusandserialbus.Parallelbususesntransmissionlinestotransmitn-bitbinaryinformationatthesametime.Itischaracterizedbyfasttransmissionspeed,butthesystemstructureismorecomplicated.Itisusedfortheconnectionbetweenvariouscomponentsinthecomputersystem;serialbussharesmulti-bitbinaryinformationOnatransmissionline,multiplebitsofbinaryinformationpassthroughthebusinchronologicalorder.Itischaracterizedbyasimplestructure,butitstransmissionspeedisrelativelyslow.Thebusmusthaveaclearspecification:Bustimingprotocol,thatis,certaintimingrulesmustbeobservedwhentransmittinginformationonthebus,suchassynchronousbustiming,asynchronousbustiming,semi-synchronousbustiming,etc.Thephysicalcharacteristicsofthebus,includingtheelectricalcharacteristicsofsignals,powersupplies,andaddresses,aswellasthemechanicalcharacteristicsofconnectionsandconnectors.Busbandwidth,itisthehighesttransferratethatthebuscanreach,anditsunitisMB/S.

Buscharacteristics

Becausethebusisasetofsignallinesconnectingvariouscomponents.Theinformationisrepresentedbythesignalonthesignalline,andtheoperationcanbeagreeduponbyagreeingonthesequenceofdifferentsignals.Thecharacteristicsofthebusareasfollows

• (1)Physicalcharacteristics:Physicalcharacteristicsarealsoknownasmechanicalcharacteristics,whichrefertosomecharacteristicsshownbythecomponentsonthebuswhentheyarephysicallyconnected,suchasplugsandsockets.Geometry,shape,numberofpinsandarrangementorder,etc.

• (2)Functionalcharacteristics:Functionalcharacteristicsrefertothefunctionofeachsignalline,suchastheaddressbususedtorepresenttheaddresscode.Thedatabusisusedtorepresentthetransmitteddata,andthecontrolbusrepresentsthecommandsandstatusofoperationsonthebus.

• (3)Electricalcharacteristics:Electricalcharacteristicsrefertothesignaldirectionofeachsignallineandtheeffectivelevelrangeofthesignal.Usually,themainequipment(suchasCPU)Thesignalsentoutiscalledtheoutputsignal(OUT),andthesignalsenttothemaindeviceiscalledtheinputsignal(IN).Generally,datasignalsandaddresssignalsdefinehighlevelaslogic1andlowlevelaslogic0.Thereisnoconventionalconventionforcontrolsignals.Forexample,WEmeanslowlevelisvalid,andReadymeanshighlevelisvalid.Thereisnouniformregulationforthehighandlowlevelrangesofdifferentbuses,andtheyareusuallyconsistentwithTTL.

• (4)Timecharacteristics:Timecharacteristicsarealsocalledlogiccharacteristics,whichrefertowhenthesignaloneachsignallineisvalidduringthebusoperation,anditisvalidthroughthissignalThetimingrelationshipagreementensuresthecorrectoperationofthebus.Inordertoimprovethescalabilityofthecomputerandtheversatilityofcomponentsandequipment,inadditiontotheon-chipbus,eachcomponentordeviceisconnectedtothebusinastandardizedform,andinformationtransmissiononthebusisrealizedinastandardizedway.Thesestandardizedconnectionformsandoperationmodesofthebusarecollectivelyreferredtoasbusstandards.SuchasISA,PCI,USBbusstandards,etc.Correspondingly,thebusesusingthesestandardsareISAbus,PCIbus,USBbus,etc.

Busclassification

Buscanbedividedintofivemajortypesaccordingtofunctionsandspecifications:

• DataBus:TransferdatathatneedstobeprocessedorneedstobestoredbackandforthbetweenCPUandRAM.

• AddressBus:UsedtospecifytheaddressofthedatastoredinRAM(RandomAccessMemory).

• ControlBus:Transmitthesignalofthemicroprocessorcontrolunit(ControlUnit)toperipheralequipment.

• ExpansionBus:Thebusfordatacommunicationbetweenexternaldevicesandthecomputerhost,suchasISAbusandPCIbus.

• LocalBus:Anexpansionbusthatreplaceshigher-speeddatatransmission.

ThedatabusDB(DataBus),addressbusAB(AddressBus)andcontrolbusCB(ControlBus)arealsocollectivelyreferredtoassystembus,whichistheusualmeaningThebusmentionedabove.

Insomesystems,thedatabusandtheaddressbusaremultiplexed,thatis,thesignalthatappearsonthebusatcertainmomentsrepresentsdataandothermomentsrepresentaddresses;andsomesystemsareseparate.Theaddressbusanddatabusofthe51seriessingle-chipmicrocomputeraremultiplexed,whilethebusinthegeneralPCisseparate.

"DataBusDB"isusedtotransmitdatainformation.Thedatabusisatwo-waythree-statebus,thatis,itcantransmitdatafromtheCPUtoothercomponentssuchasamemoryorI/Ointerface,andcanalsotransmitdatafromothercomponentstotheCPU.Thenumberofbitsofthedatabusisanimportantindicatorofthemicrocomputer,anditisusuallyconsistentwiththewordlengthofthemicro-processing.Forexample,thewordlengthoftheIntel8086microprocessoris16bits,anditsdatabuswidthisalso16bits.Itshouldbepointedoutthatthemeaningofdataisbroad.Itcanberealdata,instructioncodeorstatusinformation,andsometimesevencontrolinformation.Therefore,inactualwork,whatistransmittedonthedatabusisnotnecessarilyIt'sjustdatainthetruesense.

CommondatabusesareISA(ISAbus),EISA,VESA,PCI,etc.

"AddressbusAB"isspeciallyusedtotransmitaddresses.SincetheaddresscanonlybetransmittedfromtheCPUtotheexternalmemoryorI/Oport,theaddressbusisalwaysone-waythree-state,whichisdifferentfromthedataThebusisdifferent.ThenumberofbitsoftheaddressbusdeterminesthesizeofthememoryspacethatcanbedirectlyaddressedbytheCPU.Forexample,iftheaddressbusofan8-bitmicrocomputeris16bits,themaximumaddressablespaceis2^16=64KB,andthe16-bitmicrocomputer(x-bitprocessingThedevicereferstothenumberofbits(1,0)thatthemicroprocessorcanhandleinoneclockcycle,thatis,thewordlength).Theaddressbusis20bits,anditsaddressablespaceis2^20=1MB.Generallyspeaking,iftheaddressbushasnbits,theaddressablespaceis2^nbytes.

"ControlbusCB"isusedtotransmitcontrolsignalsandtimingsignals.SomeofthecontrolsignalsaresentbythemicroprocessortothememoryandI/Ointerfacecircuits,suchasread/writesignals,chipselectsignals,interruptresponsesignals,etc.;therearealsoothercomponentsthatarefedbacktotheCPU,suchasinterruptrequestsignals,resetSignals,busrequestsignals,equipmentreadysignals,etc.Therefore,thetransmissiondirectionofthecontrolbusisdeterminedbythespecificcontrolsignal,(information)isgenerallybidirectional,andthenumberofbitsofthecontrolbusshouldbedeterminedaccordingtotheactualcontrolneedsofthesystem.Infact,thespecificsituationofthecontrolbusmainlydependsontheCPU.

Accordingtothewayoftransmittingdata,itcanbedividedintoserialbusandparallelbus.Intheserialbus,thebinarydataissenttothedestinationdevicethroughadatalinebitbybit;thedatalinesoftheparallelbususuallyexceedtwo.CommonserialbusesincludeSPI,I2C,USBandRS232.

Accordingtowhethertheclocksignalisindependent,itcanbedividedintoasynchronousbusandanasynchronousbus.Theclocksignalofthesynchronousbusisindependentofthedata,whiletheclocksignaloftheasynchronousbusisextractedfromthedata.SPIandI2Caresynchronousserialbuses,andRS232usesasynchronousserialbuses.

Internalbus

Concurrency

• CAMAC,usedininstrumentdetectionsystem

• IndustryStandardArchitectureBus(ISA)

• ExtendedISA(EISA)

• LowPinCount(LPC)

• MicroChannel(MCA)

• MBus

• Multibus,Usedinindustrialproductionsystems

• NuBus,orIEEE1196

• OPTilocalbus,usedinearlyIntel80486motherboards

• PeripheralComponentInterconnectBus(PCI)

• S-100bus(S-100bus),orIEEE696,UsedinAltairorsimilarmicroprocessors

• SBusorIEEE1496

• VESAlocalbus(VLB,VL-bus)

• VERSAmoduleEurocardbus(VMEbus)

• STDbus(STDbus),usedforeightortenSix-bitmicroprocessorsystem

• Unibus

• Q-Bus

• PC/104

• PC/104Plus

• PC/104Express

• PCI-104

• PCIe-104

Serial

• 1-Wire

• HyperTransport

• I²C

• SerialPCI(PCIe)

• Serialperipheralinterfacebus(SPIbus)

• FireWirei.Link(IEEE1394)

Externalbus

ExternalbusreferstothecableandconnectorsystemusedtotransmitdataandcontrolspecifiedbyI/OpathtechnologySignal,inadditiontoabusterminationresistororcircuit,thisterminationresistorisusedToreducethesignalreflectioninterferenceonthecable.

Concurrency

• ATA:Disk/tapeperipheralaccessorybus,alsoknownasPATA,IDE,EIDE,ATAPI,etc.(TheoriginalATAisparallel,butseealsotherecentserialATA)

• HIPPI(HIghPerformanceParallelInterface):High-speedparallelinterface.

• IEEE-488:AlsoknownasGPIB(General-PurposeInstrumentationBus)orHPIB(Hewlett-PackardInstrumentationBus).

• PCcard:Formerlyknownasthewell-knownPCMCIA,itisoftenusedinnotebookcomputersandotherportabledevices,butsincetheintroductionofUSBandembeddednetworks,thisThebusisslowlynolongerused.

• SCSI(SmallComputerSystemInterface):smallcomputersysteminterface,disk/tapeperipheralaccessorybus.

Serial

• USBUniversalSerialBus,alargenumberofexternaldevicesusethisbus

• SerialAttachedSCSIandotherserialSCSIbuses

• SerialATA

• ControllerAreaNetwork("CANbus")

• EIA-485

• FireWire

• Thunderbolt

Computerbus

Computerbusisasetofinformationtransmissionlinesthatcanbesharedbymultiplecomponentsintime,usedtoconnectmultiplecomponentsandprovideinformationforthemExchangepath.Thebusisnotonlyasetofsignallines,inabroadsense,thebusisasetoftransmissionlinesandrelatedbusprotocols.

a.Mainboardbus

Incomputerscienceandtechnology,peopleoftendescribethebusfrequencyinMHz.Therearemanytypesofcomputerbuses.TheEnglishnameofthefrontsidebusisFrontSideBus,whichisusuallyrepresentedbyFSB,whichisthebusthatconnectstheCPUtotheNorthBridgechip.Thecomputer'sfront-sidebusfrequencyisjointlydeterminedbytheCPUandtheNorthbridgechip.

b.Harddiskbus

GenerallythereareSCSI,ATA,SATAandsoon.SATAistheabbreviationofSerialATA.WhyuseSerialATAistostartwithPATA-theshortcomingsofParallelATA.WeknowthatthedatalinesofATAorordinaryIDEharddiskswereoriginally40cables.These40cableshavedatalines,clocklines,controllines,andgroundlines.Amongthem,32datalinesaretransmittedinparallel(oneclockcycle).Cantransmit4bytesofdataatthesametime),sotherequirementsforsynchronizationareveryhigh.Thisiswhy80harddiskdatacablesmustbeusedstartingfromthePATA-66(thatis,DMA66)interface.Infact,theadded40cablesareallgroundcablesforshielding,andtheyareonlygroundedononesideofthemotherboard(donotconnectOnthecontrary,iftheshieldingeffectisreversed,theshieldingeffectwillbegreatlyreduced),andthetransmissionspeedoftheshieldedharddiskcanreach66MB/s,100MB/sandthehighest133MB/s.However,afterPATA-133,theparalleltransmissionspeedhasreacheditslimit,andthethreemajorshortcomingsofPATAarefullyexposed:thelengthofthesignallinecannotbeextended,thesignalsynchronizationisdifficulttomaintain,andthe5Vsignallineconsumesalotofpower.ThenwhythedatacableoftheSCSI-320interfacecanreachthehighspeedof320MB/s,andthecablecanbeverylong?HaveyounoticedthatSCSIhigh-speeddatalinesare"flowerlines"?Thisisnottolookgood,the"flower"partisactuallyasetofdifferentialsignallinestwistedinpairs.Thiscostisnotsomethingordinarycomputersystemsarewillingtobear.

c.Otherbuses

Otherbusesinthecomputerinclude:UniversalSerialBus(UniversalSerialBus),IEEE1394,PCI,etc..

Technicalindicators

1.Thebandwidthofthebus(busdatatransferrate)

ThebandwidthofthebusreferstotheunittimeTheamountofdatatransmittedonthebus,thatis,themaximumsteady-statedatatransmissionrateofMBtransmittedpersecond.Twofactorscloselyrelatedtothebusarethebitwidthofthebusandtheworkingfrequencyofthebus.Therelationshipbetweenthem:

Thebandwidthofthebus=theworkingfrequencyofthebus*thebitwidthofthebus/8

Orbusbandwidth=(busbitwidth/8)/buscycle

2,busbitwidth

busbitWidthreferstothenumberofbitsofbinarydatathatthebuscantransmitatthesametime,orthenumberofbitsofadatabus,thatis,theconceptofbuswidthssuchas32bitsand64bits.Thewiderthebitwidthofthebus,thegreaterthedatatransferratepersecond,andthewiderthebandwidthofthebus.

3.Theworkingfrequencyofthebus

TheworkingclockfrequencyofthebusisinMHZ.Thehighertheworkingfrequency,thefasterthebusworkingspeedandthebusbandwidth.Wider.

Reasonablecollocation

Themotherboardnorthbridgechipisresponsibleforcontactingthememory,graphicscardandothercomponentswiththelargestdatathroughput,andconnectswiththesouthbridgechip.TheCPUisconnectedtothenorthbridgechipthroughthefrontsidebus(FSB),andthenexchangesdatawiththememoryandthegraphicscardthroughthenorthbridgechip.Thefront-sidebusisthemostimportantchannelfortheCPUtoexchangedatawiththeoutsideworld.Therefore,thedatatransmissioncapabilityofthefront-sidebushasagreateffectontheoverallperformanceofthecomputer.Themaximumbandwidthofdatatransmissiondependsonthewidthandtransmissionfrequencyofallsimultaneouslytransmitteddata,thatis,databandwidth=(busfrequency×databitwidth)÷8.Thefront-sidebusfrequenciesthatcanbeachievedonthePCare266MHz,333MHz,400MHz,533MHz,800MHz.Thelargerthefront-sidebusfrequency,thegreaterthedatatransmissioncapacitybetweentheCPUandtheNorthbridgechip,andthemoretheCPUcanbefullyutilized.Function.CPUtechnologyhasdevelopedrapidly,andcomputingspeedhasincreasedrapidly,andalargefront-sidebuscanguaranteeenoughdatatobesuppliedtotheCPU,andalowerfront-sidebuswillnotbeabletosupplyenoughdatatotheCPU,whichlimitstheperformanceoftheCPU.,Becomeasystembottleneck.

Busoperation

Oneoperationprocessofthebusistocompletethetransferofinformationbetweentwomodules.Themastermodulestartstheoperationprocess,andtheotheristheslavemodule.Onlyonemainmoduleonthebuscanoccupythebusatacertaintime.

Operationstepsofthebus:

Themainmoduleappliesforbuscontrol,andthebuscontrollermakesaruling.

Operationstepsofthebus:

Themastermodulewilladdresstheslavemoduleafterobtainingthebuscontrolright,andthentheslavemodulewillconfirmthedatatransmission.

Errorcheckingofdatatransmission.

Bustimingprotocol:Thetimingprotocolcanensurethatthetwosidesofthedatatransmissionaresynchronizedinoperationandthetransmissioniscorrect.Therearethreetypesoftimingprotocols:

Synchronousbustiming:Allmodulesonthebussharethesameclockpulsetocontroltheoperationprocess.Allactionsofeachmodulearegeneratedatthebeginningoftheclockcycle,andmostactionsarecompletedinoneclockcycle.

Asynchronousbustiming:Theoccurrenceoftheoperationisdeterminedbythespecificsignalofthesourceordestinationmodule.Theoccurrenceofaneventonthebusdependsontheoccurrenceofthepreviousevent,andthetwopartiesprovidecommunicationsignalstoeachother.

Bustimingprotocol

Semi-synchronousbustiming:Thetimeintervalofeachoperationonthebuscanbedifferent,butitmustbeanintegermultipleoftheclockcycle.Theappearanceofthesignal,thesamplingandtheendarestillThepublicclockisthereference.TheISAbususesthistimingmethod.

Datatransmissiontype:dividedintosinglecyclemodeandburstmode.

Singlecyclemode:Onlyonedataistransmittedinonebuscycle.

Burstmode:Afterobtainingthecontrolofthemainline,multipledatatransmissionsarecarriedout.Whenaddressing,thefirstaddressofthedestinationisgiven,andthefirstdataisaccessed.Theaddressesofdata2,3todatanareautomaticallyaddressedbasedonthefirstaddressaccordingtocertainrules(suchasautomaticallyadding1).

Busstandard

Whydevelopabusstandard?

Itisconvenientfortheexpansionofmachinesandtheadditionofnewequipment.Thereisabusstandard,Differentmanufacturerscanproducechips,modulesandcompletemachineswithdifferentfunctionsaccordingtothesamestandardsandspecifications.Userscanchoosemodulesanddevicesproducedbydifferentmanufacturersandbasedonthesamebusstandardaccordingtotheirfunctionalrequirements.Theycanevenfollowthestandards.Designspecialmodulesandequipmentwithspecialfunctionsbyyourselftoformtheapplicationsystemyouneed.Inthisway,productsatthechiplevel,modulelevel,anddevicelevelarecompatibleandinterchangeable,sothatthemaintainabilityandexpandabilityoftheentirecomputersystemcanbefullyguaranteed.

Thetechnicalspecificationofthebusstandard?

Mechanicalstructurespecification:modulesize,busplug,busconnectorandinstallationsizehaveunifiedregulations.

Functionspecification:Eachsignalline(nameofthepin),functionandworkingprocessofeachbusmusthaveunifiedregulations.

Electricalspecifications:theeffectivelevel,dynamicconversiontime,loadcapacity,etc.ofeachsignallineofthebus.

Whichbusisstandard?

Theprocessor-mainmemorybusonthemotherboardisoftenaspecificdedicatedbus,whiletheI/ObusandbackplanebususedtoconnectvariousI/OmodulesareusuallyavailableinInteroperableindifferentcomputers.Infact,thebackplanebusandI/Obusareusuallystandardbusesandcanbeusedbymanydifferentcomputersmanufacturedbydifferentcompanies.

BusStandard-ISA

ISA(IndustrialStandardArchitecture)busisasystembusstandardestablishedbyIBMin1984fortheintroductionofPC/ATmachines.SoitisalsocalledATbus.

Mainfeatures:

(1)Support64KI/Oaddressspace,16Mmainmemoryaddressspaceaddressing,support15-levelhardinterrupt,7-levelDMAchannel.

(2)isasimplemulti-masterbus.InadditiontotheCPU,DMAcontrollers,DRAMrefreshcontrollers,andintelligentinterfacecontrolcardswithprocessorscanallbecomebusmasterdevices.

(3)Supports8typesofbustransactions:memoryread,memorywrite,I/Oread,I/Owrite,interruptresponse,DMAresponse,memoryrefresh,busarbitration.

Itsclockfrequencyis8MHz,andthereare98signallinesintotal.Thedatalineisseparatedfromtheaddressline.Thewidthofthedatalineis16bits,whichcantransmit8-bitor16-bitdata,sothemaximumdatatransferrateis16MB/s.

BusStandard-EISA

EISA(ExtendedIndustrialStanderdArchitecture)busisanopenbusstandardexpandedonthebasisofISAbus.Supportmulti-busmastercontrolandbursttransmissionmode.

Theclockfrequencyis8.33MHz.Thereare198signallinesintotal,and100lineshavebeenexpandedonthebasisof98linesoftheoriginalISAbus,whichisfullycompatiblewiththeoriginalISAbus.Ithasseparatedatalinesandaddresslines.Thedatalinewidthis32bits,with8-bit,16-bit,and32-bitdatatransmissioncapabilities,sothemaximumdatatransmissionrateis33MB/s.Thewidthoftheaddresslineis32bits,sotheaddressingcapabilityisupto232.Thatis:thesemasterdevicessuchasCPUorDMAcontrollercanaccessthe4Grangeofthemainmemoryaddressspace.

Busstandard-PCI

PCI(PeripheralComponentInterconnect)bus

isahigh-performance32-bitlocalbus.ItwasproposedbyIntelattheendof1991,andlaterjoinedwithmorethan100majorPCmanufacturerssuchasIBMandDECtoestablishthePCIGroupin1992,calledPCISIG,tocoordinateandpromotethePCIstandard.

TheI/Ointerfaceusedforhigh-speedperipheralsisconnectedtothehost.Usingitsownbusfrequencyof33MHz,thedatalinewidthis32bits,whichcanbeexpandedto64bits,sothedatatransferratecanreach132MB/s～264MB/s.

Fastspeed,supportunlimitedbursttransmissionmode,supportconcurrentwork(PCIbridgeprovidesdatabuffer,andmakesthebusindependentoftheCPU),andcanbeconnectedtoothersystembuses(suchas:ISA,EISAorMCA)isconnected,thehigh-speeddevicesinthesystemareconnectedtothePCIbus,whilethelow-speeddevicesarestillsupportedbythelow-speedI/ObusessuchasISAandEISA.Itsupportsmicroprocessor-basedconfigurationandcanbeusedinsingle-processorsystemsaswellasmulti-processorsystems.

AdvantagesandDisadvantages

Themainadvantagesofusingthebusstructure

1.Thememory-orienteddualbusstructurehashigherinformationtransmissionefficiency,Thisisitsmainadvantage.ButwhenboththeCPUandtheI/Ointerfacehavetoaccessthememory,conflictsstilloccur.

2.TheCPUisconnectedtothehigh-speedlocalmemoryandlocalI/Ointerfacethroughahigh-speedlocalbus,andtheslowerglobalmemoryandglobalI/Ointerfaceareconnectedtotheslowerglobalbus.Thus,bothhigh-speedequipmentandslow-speedequipmentaretakenintoconsideration,sothattheydonotinvolveeachother.

3.Simplifiesthehardwaredesign.Itisconvenienttoadoptthemodularstructuredesignmethod.Thebus-orientedmicrocomputerdesignonlyneedstomakecpuplug-in,memoryplug-inandI/Oplug-inaccordingtotheseregulations,andconnectthemtothebustoworkwithoutconsideringthedetailedoperationofthebus.

4.Simplifiedthesystemstructure.Thestructureofthewholesystemisclear.Therearefewconnections,andthebackplaneconnectionscanbeprinted.

5.Thesystemhasgoodscalability.Thefirstisscaleexpansion,whichonlyrequiresmoreplug-insofthesametype.Thesecondisfunctionexpansion.Thefunctionexpansiononlyneedstodesignnewplug-insinaccordancewiththebusstandard,andthereisoftennostrictrestrictiononthepositionwheretheplug-insareinsertedintothemachine.

6.Thesystemupdateperformanceisgood.Becausethecpu,memory,I/Ointerface,etc.areallconnectedtothebusaccordingtothebusprotocol,aslongasthebusisproperlydesigned,newplug-inscanbedesignedatanytimealongwiththeprogressoftheprocessorchipandotherrelatedchips.Thesystemisupdatedonthebottomboard,otherplug-insandbackplaneconnectionsgenerallydonotneedtobechanged.

7.Itisconvenientforfaultdiagnosisandmaintenance.Themainboardtestcardcaneasilyfindthefaultypartandthebustype.

Disadvantagesofthebusstructure

BecausethebusissetupbetweentheCPUandthemainmemory,andbetweentheCPUandtheI/Odevice,itimprovesThespeedandefficiencyofinformationtransmissioninthemicrocomputersystemareimproved.However,becausethereisnodirectpathbetweentheexternaldeviceandthemainmemory,theinformationexchangebetweenthemmustbetransferredthroughtheCPU,whichreducestheworkefficiencyoftheCPU(orincreasestheoccupancyrateoftheCPU.Generallyspeaking,theperipheralworkThelessCPUinterventionisrequired,thebetter.ThelessCPUintervention,thelowertheCPUoccupancyrateofthisdevice,indicatingthehigherthedegreeofintelligenceofthedevice.ThisisthemaindisadvantageoftheCPU-orienteddual-busstructure.Italsoincludes:

1.Theuseofbustransmissionistime-sharing.Whenmultiplemastersapplyfortheuseofthebusatthesametime,arbitrationofthebusmustbecarriedout.

2.Thebandwidthofthebusislimited.Ifahardwaredeviceconnectedtothebusdoesnothavearesourcecontrolmechanism,itwilleasilycauseinformationdelay(thisisfatalinsomeplaceswithstrongimmediacy).

3.Thedeviceconnectedtothebusmusthaveaninformationscreeningmechanism,anditisnecessarytojudgewhethertheinformationispassedtoitself.

Relatedinformation

Anymicroprocessormustbeconnectedtoacertainnumberofcomponentsandperipheraldevices,butifyouuseasetoflinesforeachcomponentandeachperipheraldeviceConnectdirectlywiththeCPU,thentheconnectionwillbeintricateandevendifficulttoimplement.Inordertosimplifythehardwarecircuitdesignandsimplifythesystemstructure,agroupoflinesiscommonlyused,andanappropriateinterfacecircuitisconfiguredtoconnectwithvariouscomponentsandperipheraldevices.Thisgroupofsharedconnectionlinesiscalledabus.Theuseofabusstructurefacilitatestheexpansionofcomponentsandequipment,especiallythedevelopmentofaunifiedbusstandardmakesiteasytointerconnectdifferentequipment.

Thebusinamicrocomputergenerallyincludesaninternalbus,asystembusandanexternalbus.Theinternalbusisthebusbetweentheperipheralchipsinthemicrocomputerandtheprocessor,whichisusedfortheinterconnectionatthechiplevel;whilethesystembusisthebusbetweentheplug-inboardsandthesystemboardinthemicrocomputer,andisusedforthemutualexchangeattheplug-inboardlevel.Theexternalbusisabusbetweenamicrocomputerandanexternaldevice.Asadevice,amicrocomputerexchangesinformationanddatawithotherdevicesthroughthebus.Itisusedfordevice-levelinterconnection.Inaddition,inabroadsense,computercommunicationmethodscanbedividedintoparallelcommunicationandserialcommunication,andthecorrespondingcommunicationbusesarecalledparallelbusesandserialbuses.Parallelcommunicationisfastandhasgoodreal-timeperformance,butitisnotsuitableforminiaturizedproductsduetothelargenumberofportsoccupied.Althoughtheserialcommunicationrateislow,itismoresimpleandconvenientinthemicro-processingcircuitwherethedatacommunicationthroughputisnotverylarge.Convenientandflexible.Serialcommunicationcangenerallybedividedintoasynchronousmodeandsynchronousmode.---Withthedevelopmentofmicroelectronicstechnologyandcomputertechnology,bustechnologyisalsoconstantlydevelopingandimproving,sothatthecomputerbustechnologyhasawidevarietyandeachhasitsowncharacteristics.

Thehistoryofbusdevelopment

ISAbus

(IndustryStandardArchitecture)

TheearliestPCbusItisthesystembusadoptedbyIBMinPC/XTcomputersin1981.Itisbasedonthe8-bit8088processorandiscalledPCbusorPC/XTbus.

In1984,IBMintroducedthePC/ATcomputerbasedonthe16-bitIntel80286processor,andthesystembuswasalsoexpandedto16bit,andwascalledthePC/ATbus.InordertodevelopperipheraldevicescompatiblewiththeIBMPC,theindustrygraduallyestablishedtheISA(IndustryStandardArchitecture)busbasedontheIBMPCbusspecification.

PCIbus

(PeripheralComponentInterconnect)

DuetotheslowspeedoftheISA/EISAbus,thespeedoftheCPUonceappearedHigherthanthebusspeed,theharddisk,displaycardandotherperipheraldevicescanonlysendandreceivedatathroughaslowandnarrowbottleneck,whichseriouslyaffectstheperformanceofthewholemachine.Tosolvethisproblem,whenIntelreleasedthe486processorin1992,italsoproposeda32-bitPCI(peripheralcomponentinterconnect)bus.

AGPbus

(AcceleratedGraphicsPort)

ThePCIbusisasystembusindependentoftheCPU,whichcanconnectthedisplaycard,High-speedperipheralssuchassoundcards,networkcards,andharddiskcontrollersaredirectlyhungontheCPUbus,breakingthebottleneckandmakingtheCPUperformancefullyutilized.Unfortunately,becausethePCIbushasabandwidthofonly133MB/s,itmaybemorethanenoughtodealwithmostinput/outputdevicessuchassoundcards,networkcards,andvideocards,butfor3Dgraphicscardsthathaveagrowingappetite,theyareincapableandbecomeaconstraint.Displaythebottleneckofthesubsystemandtheperformanceofthewholemachine.Therefore,thecomplementofthePCIbus-theAGPbuscameintobeing.

PCI-Express

After10yearsofrepairsandrepairs,thePCIbushasbeenunabletomeettherequirementsofcomputerperformanceenhancement.Itmustbelargerandmoreadaptable.ThenewgenerationbuswithdeeperdevelopmentpotentialisreplacedbythePCI-Expressbus.

ComparedwiththePCIbus,thePCI-Expressbuscanprovideextremelyhighbandwidthtomeettheneedsofthesystem.ThebandwidthofthePCIExpressbus2.0standardisshowninthefollowingtable:

Afterthreeandahalfgenerations(AGPbusisjustanenhancedPCIbus),theexternalbusofPCfinallydevelopedtoPCI-E4.0,Providesamuchlargerbandwidththanthepreviousbus.Asforthefuturedirectionofbusdevelopment,Ibelieveitwillappearsoonaspeople'sdemandforbandwidthcontinuestoincrease.

Terminology